Step 0: IDF project skeleton for esp32p4 with core component stubs

- Board checked with esptool: ESP32-P4 rev v1.3 (engineering silicon),
  32 MB GigaDevice flash. Rev <3 support and 32 MB set in sdkconfig.defaults.
- OTA partition layout: nvs, otadata, phy_init, ota_0/ota_1 (6 MB each,
  below 16 MB), coredump; no factory app. Partition table at 0x10000 so
  the bootloader can grow.
- App rollback enabled in the bootloader from the start.
- PROJECT_VER from git describe --tags --always --dirty.
- Empty stubs for the nine aes67_* core components; main logs version
  and chip revision.
- Built with ESP-IDF v5.5.5; not yet flashed.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

.gitignore

@@ -0,0 +1,4 @@
+build/
+sdkconfig
+sdkconfig.old
+managed_components/

CLAUDE.md

@@ -23,7 +23,8 @@ Repo: https://gitea.apointless.space/bsncubed/aes67-ESP32-P4
 - `idf.py set-target esp32p4`, `idf.py build`, `idf.py -p <PORT> flash monitor`
 - Before first build: run `esptool.py chip_id` and `esptool.py flash_id`.
   - Chip revision < v3.0 (engineering silicon, seen on some of these boards) needs `CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y`.
-  - Flash size is unconfirmed (Waveshare says 32 MB, ESPHome says 16 MB). Set it from the flash_id result.
+    Our board: **v1.3** (set in sdkconfig.defaults, min rev v1.0).
+  - Our board: **32 MB** flash (GigaDevice c8/4019). App slots must stay below 16 MB (cache mapping above 16 MB is experimental in IDF).
 - Embed `web/index.html` via `EMBED_TXTFILES` in `aes67_web`.
 
 ## Board quick reference (full details in docs)

CMakeLists.txt

@@ -0,0 +1,16 @@
+cmake_minimum_required(VERSION 3.16)
+
+# Firmware version = git describe (tags, dirty flag). Reported by esp_app_get_description()
+# and in status.fw / GET /api/ota. Re-run cmake (idf.py reconfigure) to pick up a new tag.
+execute_process(
+    COMMAND git describe --tags --always --dirty
+    WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}
+    OUTPUT_VARIABLE PROJECT_VER
+    OUTPUT_STRIP_TRAILING_WHITESPACE
+    ERROR_QUIET)
+if(NOT PROJECT_VER)
+    set(PROJECT_VER "0.0.0-nogit")
+endif()
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(aes67_p4)

components/aes67_board/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "aes67_board.c"
+                       INCLUDE_DIRS "include")

components/aes67_board/aes67_board.c

@@ -0,0 +1,7 @@
+#include "aes67_board.h"
+
+// Stub (build step 0).
+esp_err_t aes67_board_init(void)
+{
+    return ESP_OK;
+}

components/aes67_board/include/aes67_board.h

@@ -0,0 +1,7 @@
+// aes67_board: Board pin profiles (waveshare_esp32p4_eth.h, ...) and Ethernet init.
+// Core component: must not depend on main/ (project code).
+#pragma once
+
+#include "esp_err.h"
+
+esp_err_t aes67_board_init(void);

components/aes67_health/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "aes67_health.c"
+                       INCLUDE_DIRS "include")

components/aes67_health/aes67_health.c

@@ -0,0 +1,7 @@
+#include "aes67_health.h"
+
+// Stub (build step 0).
+esp_err_t aes67_health_init(void)
+{
+    return ESP_OK;
+}

components/aes67_health/include/aes67_health.h

@@ -0,0 +1,7 @@
+// aes67_health: Uptime, heap/PSRAM, temperature sensors (temps[] with min/max/warn).
+// Core component: must not depend on main/ (project code).
+#pragma once
+
+#include "esp_err.h"
+
+esp_err_t aes67_health_init(void);

components/aes67_net/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "aes67_net.c"
+                       INCLUDE_DIRS "include")

components/aes67_net/aes67_net.c

@@ -0,0 +1,7 @@
+#include "aes67_net.h"
+
+// Stub (build step 0).
+esp_err_t aes67_net_init(void)
+{
+    return ESP_OK;
+}

components/aes67_net/include/aes67_net.h

@@ -0,0 +1,7 @@
+// aes67_net: Netif setup, optional VLAN split, DSCP/PCP helpers.
+// Core component: must not depend on main/ (project code).
+#pragma once
+
+#include "esp_err.h"
+
+esp_err_t aes67_net_init(void);

components/aes67_ota/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "aes67_ota.c"
+                       INCLUDE_DIRS "include")

components/aes67_ota/aes67_ota.c

@@ -0,0 +1,7 @@
+#include "aes67_ota.h"
+
+// Stub (build step 0).
+esp_err_t aes67_ota_init(void)
+{
+    return ESP_OK;
+}

components/aes67_ota/include/aes67_ota.h

@@ -0,0 +1,7 @@
+// aes67_ota: Firmware upload, image checks, rollback self-test.
+// Core component: must not depend on main/ (project code).
+#pragma once
+
+#include "esp_err.h"
+
+esp_err_t aes67_ota_init(void);

components/aes67_ptp/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "aes67_ptp.c"
+                       INCLUDE_DIRS "include")

components/aes67_ptp/aes67_ptp.c

@@ -0,0 +1,7 @@
+#include "aes67_ptp.h"
+
+// Stub (build step 0).
+esp_err_t aes67_ptp_init(void)
+{
+    return ESP_OK;
+}

components/aes67_ptp/include/aes67_ptp.h

@@ -0,0 +1,7 @@
+// aes67_ptp: PTPv2 ordinary clock: BMCA, servo, master, multicast/hybrid, EMAC HW timestamps, stats.
+// Core component: must not depend on main/ (project code).
+#pragma once
+
+#include "esp_err.h"
+
+esp_err_t aes67_ptp_init(void);

components/aes67_sdp_sap/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "aes67_sdp_sap.c"
+                       INCLUDE_DIRS "include")

components/aes67_sdp_sap/aes67_sdp_sap.c

@@ -0,0 +1,7 @@
+#include "aes67_sdp_sap.h"
+
+// Stub (build step 0).
+esp_err_t aes67_sdp_sap_init(void)
+{
+    return ESP_OK;
+}

components/aes67_sdp_sap/include/aes67_sdp_sap.h

@@ -0,0 +1,7 @@
+// aes67_sdp_sap: SDP builder/parser and SAP announcer.
+// Core component: must not depend on main/ (project code).
+#pragma once
+
+#include "esp_err.h"
+
+esp_err_t aes67_sdp_sap_init(void);

components/aes67_syslog/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "aes67_syslog.c"
+                       INCLUDE_DIRS "include")

components/aes67_syslog/aes67_syslog.c

@@ -0,0 +1,7 @@
+#include "aes67_syslog.h"
+
+// Stub (build step 0).
+esp_err_t aes67_syslog_init(void)
+{
+    return ESP_OK;
+}

components/aes67_syslog/include/aes67_syslog.h

@@ -0,0 +1,7 @@
+// aes67_syslog: Remote syslog (esp_log hook -> queue -> UDP).
+// Core component: must not depend on main/ (project code).
+#pragma once
+
+#include "esp_err.h"
+
+esp_err_t aes67_syslog_init(void);

components/aes67_tx/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "aes67_tx.c"
+                       INCLUDE_DIRS "include")

components/aes67_tx/aes67_tx.c

@@ -0,0 +1,7 @@
+#include "aes67_tx.h"
+
+// Stub (build step 0).
+esp_err_t aes67_tx_init(void)
+{
+    return ESP_OK;
+}

components/aes67_tx/include/aes67_tx.h

@@ -0,0 +1,7 @@
+// aes67_tx: RTP sender task, PTP-paced, pull callback; optional mono sum.
+// Core component: must not depend on main/ (project code).
+#pragma once
+
+#include "esp_err.h"
+
+esp_err_t aes67_tx_init(void);

components/aes67_web/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "aes67_web.c"
+                       INCLUDE_DIRS "include")

components/aes67_web/aes67_web.c

@@ -0,0 +1,7 @@
+#include "aes67_web.h"
+
+// Stub (build step 0).
+esp_err_t aes67_web_init(void)
+{
+    return ESP_OK;
+}

components/aes67_web/include/aes67_web.h

@@ -0,0 +1,7 @@
+// aes67_web: httpd, embedded index.html, config store (cJSON in NVS), core routes.
+// Core component: must not depend on main/ (project code).
+#pragma once
+
+#include "esp_err.h"
+
+esp_err_t aes67_web_init(void);

docs/hardware-and-design-notes.md

@@ -3,7 +3,7 @@
 Core AES67 parts (PTP, TX, SDP/SAP, network/VLAN, syslog, web UI base, config schema, component layout) are in **aes67-core-base.md**. This file covers the board and the project-specific parts.
 
 ## Board: Waveshare ESP32-P4-ETH (bought as ESP32-P4-POE-ETH, i.e. with PoE add-on module)
-- ESP32-P4, dual-core RISC-V HP @ 360 MHz + LP core, 32 MB in-package PSRAM, NOR flash (Waveshare wiki says 32 MB, ESPHome says 16 MB — check with `esptool.py flash_id`)
+- ESP32-P4, dual-core RISC-V HP @ 360 MHz + LP core, 32 MB in-package PSRAM, 32 MB NOR flash (confirmed with `esptool.py flash_id`)
 - **No Wi-Fi/BT** on this variant (the -WIFI6- variant adds an ESP32-C6). Ethernet only.
 - Ethernet: IP101GRI PHY, RMII, 100 Mb, 50 MHz ref clock from PHY (25 MHz xtal), PHY addr 1
   - REF_CLK 50 (EMAC_CLK_EXT_IN), TX_EN 49, TXD0 34, TXD1 35, CRS_DV 28, RXD0 29, RXD1 30, MDC 31, MDIO 52, PHY_RST/power 51

main/CMakeLists.txt

@@ -0,0 +1,3 @@
+idf_component_register(SRCS "main.c"
+                       INCLUDE_DIRS "."
+                       REQUIRES esp_app_format esp_hw_support)

main/main.c

@@ -0,0 +1,17 @@
+#include "esp_app_desc.h"
+#include "esp_chip_info.h"
+#include "esp_log.h"
+
+static const char *TAG = "main";
+
+void app_main(void)
+{
+    const esp_app_desc_t *app = esp_app_get_description();
+    esp_chip_info_t chip;
+    esp_chip_info(&chip);
+
+    ESP_LOGI(TAG, "%s %s (IDF %s, built %s %s)",
+             app->project_name, app->version, app->idf_ver, app->date, app->time);
+    ESP_LOGI(TAG, "chip rev v%d.%d, %d cores",
+             chip.revision / 100, chip.revision % 100, chip.cores);
+}

partitions.csv

@@ -0,0 +1,11 @@
+# OTA layout: two app slots, no factory app. Fixed from step 0 on; do not change later.
+# 32 MB flash, but app slots must stay below 16 MB (no cache mapping above it). 16-32 MB is free for data.
+# Partition table at 0x10000 (not 0x8000) leaves the bootloader room to grow (0x2000-0x10000).
+# NVS sits outside the app slots so config survives updates.
+# Name,    Type, SubType,  Offset,   Size
+nvs,       data, nvs,      0x11000,  0x6000
+otadata,   data, ota,      0x17000,  0x2000
+phy_init,  data, phy,      0x19000,  0x1000
+ota_0,     app,  ota_0,    0x20000,  0x600000
+ota_1,     app,  ota_1,    0x620000, 0x600000
+coredump,  data, coredump, 0xc20000, 0x10000

sdkconfig.defaults

@@ -0,0 +1,18 @@
+CONFIG_IDF_TARGET="esp32p4"
+
+# OTA layout (partitions.csv): two app slots, no factory
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
+# Bootloader had only 6% free below 0x8000; moved so it can grow (e.g. secure boot) without a relayout
+CONFIG_PARTITION_TABLE_OFFSET=0x10000
+
+# Rollback lives in the bootloader, which is only ever flashed over USB: enable it from the start
+CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE=y
+
+# Board has engineering silicon v1.3 (esptool chip_id). Rev <3 binaries don't run on rev 3 and vice versa.
+CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y
+CONFIG_ESP32P4_REV_MIN_100=y
+
+# 32 MB flash (esptool flash_id: GigaDevice c8/4019). App slots stay below 16 MB;
+# cache mapping above 16 MB is experimental in IDF.
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y