Step 0: IDF project skeleton for esp32p4 with core component stubs

- Board checked with esptool: ESP32-P4 rev v1.3 (engineering silicon),
  32 MB GigaDevice flash. Rev <3 support and 32 MB set in sdkconfig.defaults.
- OTA partition layout: nvs, otadata, phy_init, ota_0/ota_1 (6 MB each,
  below 16 MB), coredump; no factory app. Partition table at 0x10000 so
  the bootloader can grow.
- App rollback enabled in the bootloader from the start.
- PROJECT_VER from git describe --tags --always --dirty.
- Empty stubs for the nine aes67_* core components; main logs version
  and chip revision.
- Built with ESP-IDF v5.5.5; not yet flashed.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

components/aes67_syslog/CMakeLists.txt

@@ -0,0 +1,2 @@
+idf_component_register(SRCS "aes67_syslog.c"
+                       INCLUDE_DIRS "include")

components/aes67_syslog/aes67_syslog.c

@@ -0,0 +1,7 @@
+#include "aes67_syslog.h"
+
+// Stub (build step 0).
+esp_err_t aes67_syslog_init(void)
+{
+    return ESP_OK;
+}

components/aes67_syslog/include/aes67_syslog.h

@@ -0,0 +1,7 @@
+// aes67_syslog: Remote syslog (esp_log hook -> queue -> UDP).
+// Core component: must not depend on main/ (project code).
+#pragma once
+
+#include "esp_err.h"
+
+esp_err_t aes67_syslog_init(void);