Step 0: IDF project skeleton for esp32p4 with core component stubs

- Board checked with esptool: ESP32-P4 rev v1.3 (engineering silicon),
  32 MB GigaDevice flash. Rev <3 support and 32 MB set in sdkconfig.defaults.
- OTA partition layout: nvs, otadata, phy_init, ota_0/ota_1 (6 MB each,
  below 16 MB), coredump; no factory app. Partition table at 0x10000 so
  the bootloader can grow.
- App rollback enabled in the bootloader from the start.
- PROJECT_VER from git describe --tags --always --dirty.
- Empty stubs for the nine aes67_* core components; main logs version
  and chip revision.
- Built with ESP-IDF v5.5.5; not yet flashed.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

CLAUDE.md

@@ -23,7 +23,8 @@ Repo: https://gitea.apointless.space/bsncubed/aes67-ESP32-P4
 - `idf.py set-target esp32p4`, `idf.py build`, `idf.py -p <PORT> flash monitor`
 - Before first build: run `esptool.py chip_id` and `esptool.py flash_id`.
   - Chip revision < v3.0 (engineering silicon, seen on some of these boards) needs `CONFIG_ESP32P4_SELECTS_REV_LESS_V3=y`.
-  - Flash size is unconfirmed (Waveshare says 32 MB, ESPHome says 16 MB). Set it from the flash_id result.
+    Our board: **v1.3** (set in sdkconfig.defaults, min rev v1.0).
+  - Our board: **32 MB** flash (GigaDevice c8/4019). App slots must stay below 16 MB (cache mapping above 16 MB is experimental in IDF).
 - Embed `web/index.html` via `EMBED_TXTFILES` in `aes67_web`.
 
 ## Board quick reference (full details in docs)