bsncubed
6090ceb239
- aes67_ptp/ptp_hw.c: start the EMAC IEEE 1588 clock (IDF
ETH_MAC_ESP_CMD_PTP_ENABLE) and additionally enable snapshots for
PTP over UDP/IPv4 (IDF only enables PTP over Ethernet/L2). An RX hook
on the driver's info input path records {type, seq, sourcePortId, HW
timestamp} of port-319 PTPv2 event messages, then hands every frame to
lwIP unchanged.
- aes67_ptp.c: temporary 3.1 logger joins 224.0.1.129:319/320 and pairs
Sync HW RX timestamps with Follow_Up origin timestamps.
- Checked against linuxptp ptp4l (-4 -E -H, Intel igb) as GM: every Sync
has a HW timestamp; HW Sync intervals track the GM intervals with a
constant -39.8 us/s (+-0.3 us), i.e. local clock -39.8 ppm vs GM.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
#include "aes67_board.h"
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#include "aes67_health.h"
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#include "aes67_net.h"
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#include "aes67_ota.h"
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#include "aes67_ptp.h"
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#include "aes67_syslog.h"
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#include "aes67_tx.h"
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#include "aes67_web.h"
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#include "esp_app_desc.h"
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#include "esp_chip_info.h"
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#include "esp_log.h"
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#include "project_cfg.h"
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static const char *TAG = "main";
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void app_main(void)
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{
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const esp_app_desc_t *app = esp_app_get_description();
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esp_chip_info_t chip;
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esp_chip_info(&chip);
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ESP_LOGI(TAG, "%s %s (IDF %s, built %s %s)",
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app->project_name, app->version, app->idf_ver, app->date, app->time);
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ESP_LOGI(TAG, "chip rev v%d.%d, %d cores",
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chip.revision / 100, chip.revision % 100, chip.cores);
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project_cfg_defaults();
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esp_eth_handle_t eth;
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ESP_ERROR_CHECK(aes67_board_eth_init(ð));
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ESP_ERROR_CHECK(aes67_net_init(eth));
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ESP_ERROR_CHECK(aes67_health_init());
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ESP_ERROR_CHECK(aes67_ptp_init());
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ESP_ERROR_CHECK(aes67_ptp_start(eth));
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ESP_ERROR_CHECK(aes67_tx_init());
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ESP_ERROR_CHECK(aes67_syslog_init());
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project_cfg_register();
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ESP_ERROR_CHECK(aes67_ota_init());
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ESP_ERROR_CHECK(aes67_web_start());
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}
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