aes67-ESP32-P4/components/aes67_ptp/CMakeLists.txt at 41103e3b5eb9b9521c63d2a55f1771b4cb9543df - aes67-ESP32-P4 - Gitea: Git with a cup of tea

bsncubed/aes67-ESP32-P4

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bsncubed e2f4d81326 Step 3.2: TimeReceiver measurement (GM selection, Delay_Req/Resp, path delay)

- ptp_clock.c replaces the 3.1 logger: UDP/IPv4 multicast, E2E.
  Announce: IEEE 1588 dataset comparison picks the best GM, dropped after
  announceReceiptTimeout x its announce interval. Sync/Follow_Up (two-step
  and one-step) with HW t2 and correctionField. Delay_Req sent as a raw
  frame (DSCP ptp.dscp, TTL 1, clockIdentity = EUI-64 from MAC) with HW
  TX timestamp t3, randomised at the GM's Delay_Resp interval; Delay_Resp
  matched on requestingPortIdentity + seq.
- Path delay corrected for offset drift between t2 and t3 (rate from
  consecutive Syncs) so it is right before the clock is syntonised.
- ptp_hw: ptp_hw_send_event() builds Eth/IPv4/UDP 319 and returns the HW
  TX timestamp.
- Verified vs ptp4l (i210 GM, HP 2530 non-PTP switch, PC 1G / board 100M):
  GM selected, path delay settles at ~10.3 us and stays flat, rate
  -39.8 +-0.4 ppm, offset drifts at -40 us/s (no servo yet).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

2026-09-24 23:50:46 +10:00

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234 B

CMake

Raw Blame History

 idf_component_register(SRCS "aes67_ptp.c" "ptp_clock.c" "ptp_hw.c"
                        INCLUDE_DIRS "include"
                        REQUIRES esp_eth
                        PRIV_REQUIRES aes67_web esp_netif esp_timer lwip hal soc)