After a clock step, status.ptp showed the whole step (~1.79e18 ns) as
offset_ns until the next Sync, and the 60 s summary reported it as
max |offset|. Offset is reset to 0 and the summary restarts on a step.
Verified: status goes 0 -> pull-in values; first summary max 24960 ns.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
- aes67_sdp_sap: aes67_sdp_build() builds the AES67 SDP (RFC 4566 +
RFC 7273) with the same lines and order as the web UI preview;
GET /stream.sdp serves it as application/sdp.
- aes67_ptp: public aes67_ptp_gm_id(), aes67_ptp_locked(),
aes67_ptp_now_ns(). Clock IDs are now uppercase (RFC 7273 style), also
in status.ptp, which the UI copies into ts-refclk.
- aes67_net: aes67_net_netif() returns the AES67 interface.
- Verified on board: /stream.sdp byte-identical to the UI's sdp() for
the same config/status; mono, L16, ptime 0.333, ttl 8, clk_offset
4294967295 and session_ver all follow the config.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
- ptp_clock_status() adds status.ptp: state (LISTENING / UNCALIBRATED /
SLAVE), locked, gm_id, offset_ns, freq_ppb, path_delay_ns +
path_delay_sd_ns (window of 64, from lock on), steps_removed,
gm_time/freq_traceable, version, own_class (255 slave / 248 auto,
master), clock_id, gm_class/accuracy/p1/p2, sync_avg/min/max_ms and
sync_jitter_us (HW Sync intervals), announce_avg_ms, delay_req/resp
counters, hw_ts, window. Snapshot under a mutex shared with the PTP task.
- Per-Sync log moved to debug; info level logs state changes plus a
60 s summary (max |offset|, freq, delay).
- Verified vs ptp4l: LISTENING -> UNCALIBRATED -> SLAVE in ~35 s;
locked offset within a few hundred ns, delay 10.27 us +-0.20 us,
Delay_Req/Resp 69/69, Sync avg 1000.097 ms, Announce avg 2000 ms.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
- ptp_hw: ptp_hw_adj_freq() (ETH_MAC_ESP_CMD_ADJ_PTP_TIME, absolute ppb
vs nominal, clamped +-500 ppm, retried while the addend update is
busy) and ptp_hw_step() (read + write time).
- ptp_clock: first Sync after a GM is selected seeds the integral with
the measured rate and steps the clock; then linuxptp-style PI (kp/ki
from the Sync interval: 0.7/0.3 at 1 s). Re-step above 1 ms. Locked
after 8 Syncs with |offset| < 1 us, unlocked after 3 above; GM change
or loss unlocks and keeps the frequency (holdover).
- Verified vs ptp4l: stepped to GM time, locked after ~19 s; locked
offset within +-510 ns (mostly < 300 ns), correction +39.9 ppm
(crystal -39.8 ppm), path delay ~10.2 us.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
- ptp_clock.c replaces the 3.1 logger: UDP/IPv4 multicast, E2E.
Announce: IEEE 1588 dataset comparison picks the best GM, dropped after
announceReceiptTimeout x its announce interval. Sync/Follow_Up (two-step
and one-step) with HW t2 and correctionField. Delay_Req sent as a raw
frame (DSCP ptp.dscp, TTL 1, clockIdentity = EUI-64 from MAC) with HW
TX timestamp t3, randomised at the GM's Delay_Resp interval; Delay_Resp
matched on requestingPortIdentity + seq.
- Path delay corrected for offset drift between t2 and t3 (rate from
consecutive Syncs) so it is right before the clock is syntonised.
- ptp_hw: ptp_hw_send_event() builds Eth/IPv4/UDP 319 and returns the HW
TX timestamp.
- Verified vs ptp4l (i210 GM, HP 2530 non-PTP switch, PC 1G / board 100M):
GM selected, path delay settles at ~10.3 us and stays flat, rate
-39.8 +-0.4 ppm, offset drifts at -40 us/s (no servo yet).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
- aes67_ptp/ptp_hw.c: start the EMAC IEEE 1588 clock (IDF
ETH_MAC_ESP_CMD_PTP_ENABLE) and additionally enable snapshots for
PTP over UDP/IPv4 (IDF only enables PTP over Ethernet/L2). An RX hook
on the driver's info input path records {type, seq, sourcePortId, HW
timestamp} of port-319 PTPv2 event messages, then hands every frame to
lwIP unchanged.
- aes67_ptp.c: temporary 3.1 logger joins 224.0.1.129:319/320 and pairs
Sync HW RX timestamps with Follow_Up origin timestamps.
- Checked against linuxptp ptp4l (-4 -E -H, Intel igb) as GM: every Sync
has a HW timestamp; HW Sync intervals track the GM intervals with a
constant -39.8 us/s (+-0.3 us), i.e. local clock -39.8 ppm vs GM.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
- aes67_web/cfg.c: cfg_register(group, defaults, validate, apply),
cfg_override_defaults() for project defaults, cfg_get(). Stored values
are loaded on register and merged over defaults (known keys, matching
types). NVS keeps only keys that differ from defaults, one JSON string
per group, so new firmware defaults still reach untouched settings.
- POST /api/config: type check against defaults, per-group validation,
nothing stored unless every group passes; 400 "group.key: reason".
Unknown keys/groups are ignored. Returns the new config.
- Core groups registered by their components with the UI's ranges:
ptp (aes67_ptp), aes67 (aes67_tx, incl. multicast range and mono_sum
=> 1 channel), net/inet (aes67_net), log (aes67_syslog).
- Project: PROJECT.def overrides (hostname p4-aes67, name P4 AES67) and
the "source" group in main/project_cfg.c.
- Config is stored only; nothing is applied live yet.
- Verified on board: defaults, valid save, 8 rejected values (nothing
stored), persistence across reboot, restore to defaults.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
- Board checked with esptool: ESP32-P4 rev v1.3 (engineering silicon),
32 MB GigaDevice flash. Rev <3 support and 32 MB set in sdkconfig.defaults.
- OTA partition layout: nvs, otadata, phy_init, ota_0/ota_1 (6 MB each,
below 16 MB), coredump; no factory app. Partition table at 0x10000 so
the bootloader can grow.
- App rollback enabled in the bootloader from the start.
- PROJECT_VER from git describe --tags --always --dirty.
- Empty stubs for the nine aes67_* core components; main logs version
and chip revision.
- Built with ESP-IDF v5.5.5; not yet flashed.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
bsncubed